1. Field of the Invention
Embodiments of the present invention relate to, but are not limited to, electronic devices and, in particular, to the field of electronic device manufacturing.
2. Description of Related Art
In the current state of electronics, horizontal die shrinkage has proceeded at a relentless pace, fueled by, in some instances, roughly ⅓ pitch reduction per generation. By contrast, vertical shrinkage has progressed much more slowly due to various reasons. One obstacle that has impeded vertical shrinkage is the shortcomings associated with various fabrication operations, for example, polishing operations.
For instance, in the field of flash memory devices, several polishing operations may be performed during the fabrication process. Each of the polishing operations is typically directed to planarizing or smoothing specific component or components on the silicon substrate. Unfortunately, because the silicon substrates are often characterized by a widely varied topography that includes different components made of different materials at varying concentrations, efficiently polishing these surfaces is often difficult.
For example, the silicon substrates used to form the foundation for these flash memory devices will typically be embedded with numerous isolation trenches (e.g., shallow trench isolation) that dot the landscape of the substrate at varying concentrations. The isolation trenches are typically made of oxides. The concentration level of the isolation trenches in a particular region will depend on whether the region is dedicated to, for example, flash memory arrays or other structures. The silicon substrate may also include other components of varying concentration including poly components such as poly-1 or floating gates for the flash memory cells. The combination of having multiple components made of different materials at varying concentrations on the substrate surfaces make polishing of these surfaces difficult to control.
Other factors that prevent some of the polishing operations from being an efficient means of planarizing the surfaces of the silicon substrates are the limitations of one or more of the polishing processes. For example, in flash memory fabrication, two of the polishing operations performed may include shallow trench isolation (STI) and self-aligned poly (SAP) polish operations. These polishing operations are primarily performed in order to polish or planarize specific components. For example, the general goal of the STI polish is to polish oxide pillars used to form shallow trench isolation (STI) while the general goal of the SAP polish is to polish poly-1 (floating gate).
Although each of the polishing processes is intended to polish specific components (e.g., STI polish for polishing oxide and SAP for polishing poly-1 or floating gates), the limited selectivity of one or more of these conventional polishing processes may prevent the processes from polishing only their intended component. To illustrate, in a typical SAP polishing process, both poly as well as oxide materials are typically removed.
As a result of these various factors, the ability to produce high quality poly components, such as poly-1, with a high yield is often difficult, particularly as the size of the devices (e.g., flash memory devices) continues to shrink. If the polish of poly-1 is overdone with a conventional process, the poly film and the oxide pillar may be too thin to protect the device from pitting. On the other hand, if the polish of poly-1 is insufficient, there may be excess poly remaining on top of oxide, which may result in shorting or leakage of the device.
Forming poly components with a smooth surface is generally an important factor in forming a defect free thin vertical profile memory device. For instance, when conventional polishing methods (e.g., conventional SAP polish) are used for polishing poly components, they will produce poly components with surface roughness having root mean square (RMS) values of about 5 Å or greater. Because of this surface roughness, the ability to form defect free components on top of the rough surface (e.g., thin silicon oxide/nitride and poly-2 on top of the poly-1) will be compromised particularly as device sizes continue to shrink.
In addition to the problem of surface roughness, other limitations of conventional polish processes include, for example, the presence of microscratches and polish residue on the surface of the silicon substrate after these processes have been completed. The presence of these defects may further limit the manufacturing yields of the overall fabrication process.